In a computer system, a bus is the means by which the electrical signals are communicated back and forth between a central processor, memory, and other devices such as input and output adapters. In a uniprocessor computer system, the bus may simply be a plurality of electrical conductors linking the various components of the system. However, in multiprocessor and other more sophisticated computer systems, the bus may become more complex and play an active role in directing the various signals between the components of the computer system, usually for the purpose of obtaining greater data throughput or speed of operation.
One of the significant restrictions in the operation of a modern high speed computer is the memory access time of main memory. The memory access time is that time required for the memory to retrieve the information from its internal storage after it has received a read address signal. Since a high percentage of data processing activities in a computer system involves reading information from memory, the cumulative amount of memory access time involved in typical data processing activities can be significant. The cumulative effect of the waiting during access time periods is to reduce the data throughput of the computer system. In a uniprocessor computer system, the system is inactive during the memory access time because the processor is waiting on a response from the memory during the memory access time. In a uniprocessor system, this is not particularly a problem because there is nothing else which the system could be doing during the access time period. However, in multiprocessor systems, the other processors in the system could use the access time periods to conduct other activities, and thereby increase the throughput of the system.
These problems have been recognized and, as a result, split transaction buses have been devised. In a split transaction bus, the bus is arranged to communicate a read address signal from the initiator (e.g. processor) to the responder (e.g. memory) in a separate transaction from that transaction which is delayed in time during which the addressed memory transfers or communicates the read data information from its internal memory back to the initiator. During the time period which elapses between the read address signal and the response from the memory, the other processors in the computer system are communicating other signals to other components of the system over the bus.
In order to avoid the confusion resulting from conflicting communications between the various components of the computer system, an arbitration technique is necessary in each split transaction bus. The arbitration technique determines which one of the particular components of the system has exclusive access to the bus at any particular time. The time intervals during which information can be communicated over the bus are known as bus cycles. In order to resolve competing requests to use the bus, each of the components of the system must be assigned a priority.
One typical approach to bus arbitration is known as activity arbitration, in which a higher priority system component is given exclusive access to the bus for a sufficient number of bus cycles or time in order to conclude any particular activity. The disadvantage of activity arbitrated buses is that the higher priority component may retain access to the bus for a sufficiently long time period and prevent other components from being able to transfer information, thereby losing that information.
Another type of arbitration technique is cycle arbitration, in which each and every cycle of the bus is individually arbitrated. The disadvantage of cycle arbitration is that an excessive amount of time is consumed in individually arbitrating each and every cycle, which can result in a reduced information throughput.
Cycle arbitration is particularly time consuming on systems utilizing centralized arbitration. In centralized arbitration systems, a single processor or other component resolves all competing requests for use of the bus and determines which of the individual components is given access to the bus. Centralized arbitration usually requires the competing system components to communicate request signals to the centralized arbiter, and the centralized arbiter to communicate the signals giving a particular component access to the bus after the arbitration has been determined. This process, known as "handshaking", also consumes time during which no usable information can be communicated over the bus. Such centralized arbitration techniques therefore also tend to reduce the capacity for data transfer, known as "bandwidth" of the bus.
Distributed arbitration techniques have been devised to avoid the problems associated with centralized arbitration. In a distributed arbitration system, each individual component of the computer system includes its own circuitry or logic to arbitrate the requests from all of the system components and determine which component is given exclusive access to the bus during a particular bus cycle. Distributed arbitration techniques usually involve less time consumptive activities on the bus itself and increase the capacity of the bus.
At the present time, synchronous buses also contribute to higher bus capacity. A synchronous bus is one in which all information transfers take place in synchronism with a single clock signal. An asynchronous bus is one in which the activities on the bus are not clocked at regular intervals. With a synchronous bus, there will generally be a higher information capacity because the clocked synchronism of all transfers of information operate on the assumption that the component receiving the information will have in fact received it. In contrast, an asynchronous bus requires that the component receiving the information send back a signal acknowledging its receipt. The separate acknowledgement signal also utilizes bus capacity without contributing to data throughput. So long as memory cycle times, that is the memory access time plus that additional minimum time required to respond to the next successive read address signal, are substantially greater than the bus cycle time, a higher data throughput will be obtained from synchronous buses than from asynchronous buses. Traditionally, synchronous buses have also been more reliable because the operation of the bus can be checked by sampling signals at given points in time and looking for inconsistencies in the sampled signal. Lastly, and perhaps most importantly, synchronous buses allow the implementation of sophisticated arbitration techniques. In an asynchronous bus, there is very little, if any, arbitration, since requests for use of the bus will be resolved on a basis of which request is received first in time. In synchronous buses, more sophisticated determinations can be implemented because requests are sampled at selected fixed points in time rather than aperiodically, and competing requests can be resolved on the basis of priority of importance assigned to the particular system component generating the request.